Power Considerations in Network Processor Design
نویسندگان
چکیده
Network processors are commonly implemented as systems-on-a-chip with multiple processors, caches, memory interfaces and I/O components on a single chip. Networking workloads lend themselves to exploiting high levels of parallelism with these chipmultiprocessors. The constraints of such a system lie in the maximum chip area and the maximum power consumption that are permissible for economic and technical reasons. We develop an analytic performance model that captures the processing performance and power consumption of such a system. Using a variety of metrics, we explore the design space of network processors and show the performance impact of different system and memory configurations.
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